Silicon Labs /Series1 /EFM32GG11B /EFM32GG11B820F2048IL120 /QSPI0 /RDDATACAPTURE

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Interpret as RDDATACAPTURE

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (BYPASS)BYPASS 0DELAY0 (DQSENABLE)DQSENABLE 0DDRREADDELAY

Description

Read Data Capture Register

Fields

BYPASS

Bypass the Adapted Loopback Clock Circuit

DELAY

Read Delay

DQSENABLE

DQS Enable Bit

DDRREADDELAY

DDR Read Delay

Links

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